1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly to an array substrate including a thin film transistor having improved properties and a method of fabricating the array substrate.
2. Discussion of the Related Art
Since a liquid crystal display (LCD) device has characteristics of light weight, thinness and low power consumption, LCD devices have been widely used. Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
Generally, the LCD device is manufactured through an array substrate fabricating process, a color filter substrate fabricating process and a cell process. In the array substrate fabricating process, array elements, such as a TFT and a pixel electrode, are formed on a first substrate. In the color filter substrate fabricating process, a color filter and a common electrode are formed on a second substrate. In a cell process, the first and second substrates are attached to each other with a liquid crystal interposed therebetween.
FIG. 1 is an exploded perspective view of the related art LCD device. The LCD device includes first and second substrates 12 and 22, and a liquid crystal layer 30. The first and second substrates 12 and 22 face each other, and the liquid crystal layer 30 is interposed therebetween.
The first substrate 12 includes a gate line 14, a data line 16, a TFT “Tr”, and a pixel electrode 18. The gate line 14 and the data line 16 cross each other such that a region is formed between the gate and data lines 14 and 16 and is defined as a pixel region “P”. The TFT “Tr” is formed at a crossing portion between the gate and data lines 14 and 16, and the pixel electrode 18 is formed in the pixel region “P” and connected to the TFT “Tr”.
The second substrate 22 includes a black matrix 25, a color filter layer 26, and a common electrode 28. The black matrix 25 has a lattice shape to cover a non-display region of the first substrate 12, such as the gate line 14, the data line 16, the TFT “Tr”. The color filter layer 26 includes first, second, and third sub-color filters 26a, 26b, and 26c. Each of the sub-color filters 26a, 26b, and 26c has one of red, green, and blue colors R, G, and B and corresponds to the each pixel region “P”. The common electrode 28 is formed on the black matrix 25 and the color filter layers 26 and over an entire surface of the second substrate 22. The first substrate 12, which includes the TFT “Tr”, the pixel electrode 18 and so on, may be referred to as an array substrate 10, and the second substrate 22, which includes the color filter layer 26, the common electrode 28 and so on, may be referred to as a color filter substrate 20.
Although not shown, to prevent the liquid crystal layer 30 from leaking, a seal pattern may be formed along edges of the first and second substrates 12 and 22. First and second alignment layers may be formed between the first substrate 12 and the liquid crystal layer 30 and between the second substrate 22 and the liquid crystal layer 30. A polarizer may be formed on an outer surface of the first and second substrates 12 and 22.
The LCD device further includes a backlight assembly (not shown) under the first substrate 12 to supply light to the liquid crystal layer 30. When a scanning signal is applied to the gate line 14 to control the TFT “Tr”, a data signal is applied to the pixel electrode 18 through the data line 16 such that the electric field is induced between the pixel and common electrodes 18 and 28. As a result, the LCD device produces images using the light from the backlight assembly.
FIG. 2 is a cross-sectional view of one pixel region of an array substrate for the related art LCD device. Referring to FIG. 2, a gate line (not shown) and a data line 73 are disposed on a substrate 59. The gate line and the data line 73 cross each other to define a pixel region P. A gate electrode 60 connected to the gate line is disposed in the pixel region P and on the substrate 59. A gate insulating layer 68 is disposed on the gate line and the gate electrode 60. A semiconductor layer 70 including an active layer 70a and an ohmic contact layer 70b is disposed on the gate insulating layer 68 to correspond to the gate electrode 60. A source electrode 76 and a drain electrode 78 are disposed on the ohmic contact layer 70b. The source electrode 76 is connected to the data line 73, and the drain electrode 78 is spaced apart from the source electrode 76. The gate electrode 60, the gate insulating layer 68, the semiconductor layer 70, the source electrode 76 and the drain electrode 78 constitute a TFT Tr. Since the semiconductor layer 70 and the source and drain electrodes 76 and 78 are formed through different mask process, the source and drain electrodes 76 and 78 cover both ends of the semiconductor layer 70, respectively.
A passivation layer 86 including a drain contact hole 80 is disposed on the data line 73 and the TFT Tr. The drain contact hole 80 exposes a portion of the drain electrode 78. A pixel electrode 88 is disposed on the passivation layer 86 in each pixel region P and contacts the drain electrode 78 through the drain contact hole 87.
These elements of the array substrate are formed by a photolithography process. The photolithography process may be referred to as a mask process. The mask process includes a step of forming a photoresist (PR) layer on an objective layer, a step of exposing the PR layer to light using a first mask, a step of developing the exposed PR layer to form a PR pattern, a step of etching the objective layer using the PR pattern as an etching mask to form a desired pattern, and a step of stripping the PR pattern. The PR material for the PR layer is classified into a positive type and a negative type. In the positive type, exposed portion are developed. On the contrary, in the negative type, exposed portions remain to form the PR pattern.
A fabricating method of the array substrate show in FIG. 2 will be explained below.
A first metal layer (not shown) is formed on the substrate 59 by depositing a first metallic material. The first metal layer is patterned by a first mask process to the gate line and the gate electrode 60. Next, the gate insulating layer 68 is formed by depositing or coating a first insulating material. Next, an intrinsic amorphous silicon layer (not shown) and an impurity-doped amorphous silicon layer (not shown) are sequentially formed on the gate insulating layer 68 by depositing intrinsic amorphous silicon and impurity-doped amorphous silicon. The intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer are patterned by a second mask process to form the semiconductor layer 70 including the active layer 70a and the ohmic contact layer 70b. 
Next, a second metal layer (not shown) is formed on the semiconductor layer 70 by depositing a second metallic material. The second metal layer is patterned by a third mask process to form the data line 73, the source electrode 76 and the drain electrode 78. A center portion of the ohmic contact layer 70b is removed using the source and drain electrodes 76 and 78 as an etching mask such that a center portion of the active layer 70a is exposed. The gate electrode 60, the gate insulating layer 68, the semiconductor layer 70, the source electrode 76 and the drain electrode 78 constitute a TFT Tr.
Next, the passivation layer 86 is formed on the data line 73 and the TFT Tr by depositing or coating a second insulating material. The passivation layer 86 is patterned by a fourth mask process to form the drain contact hole 80. Next, a transparent conductive material layer (not shown) is formed on the passivation layer 86 by depositing a transparent conductive material. The transparent conductive material layer is patterned by a fifth mask process to form the pixel electrode 88.
Namely, the array substrate in FIG. 2 is fabricated by a five mask process. As a number of the mask process is increased, production costs are increase and production yield is decreased.
To resolve these problems, an array substrate fabricated by a four mask process is introduced. FIG. 3 is a cross-sectional view of one pixel region of an array substrate for the related art LCD device.
Referring to FIG. 3, after forming the gate line (not shown) and the gate electrode 105, an insulating material, intrinsic amorphous silicon, impurity-doped amorphous silicon, and a metallic material are sequentially deposited to form the gate insulating layer 110, an intrinsic amorphous silicon layer (not shown), an impurity-doped amorphous silicon layer (not shown), and a metallic material layer. The metallic material layer, the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer are patterned by a single mask process, where a refractive exposing mask or a half-tone mask is used, to form the semiconductor layer 120, which includes the active layer 120a and the ohmic contact layer 120b, the data line 127, the source electrode 130 and the drain electrode 135. Since the semiconductor layer 120, the data line 127, the source electrode 130 and the drain electrode 135 in the array substrate shown in FIG. 3 are formed by a single mask process, the array substrate in FIG. 3 can be fabricated by a four mask process.
Unfortunately, there are some problems on the array substrate fabricated by the fourth mask process. In the four mask process, since the semiconductor layer 120, the data line 127, the source electrode 130 and the drain electrode 135 are formed by a single mask process using a refractive exposing mask or a half-tone mask, ends 121 of the active layer 120a is not covered by the source and drain electrodes 130 and 135. Light from an exterior space is irradiated into the ends 121 of the active layer 120a such that problems, for example, photo-current leakage, are generated in the TTFT Tr.
In addition, an active pattern 122a and an ohmic contact pattern 122b are formed under the data line 127. Light from the backlight unit under the array substrate is irradiated on the active pattern 122a such that problems, for example, wavy noise, are generated. As a result, displaying image quality is deteriorated.
Furthermore, since the active pattern 122a protrudes beyond the data line 127 and has a width greater than the data line 127, an aperture ratio is reduced. The pixel electrode should have a distance from the data line. Namely, referring again to FIG. 2, to avoid an electrical interference between the data line 73 and the pixel electrode 88, the pixel electrode 88 has a first distance d1 from the data line 73. Referring to FIG. 3, since there is the active pattern 122a, which protrudes beyond the data line 127, the pixel electrode 150 should have a second distance d2, which is greater than the first distance d1 (of FIG. 2), from the data line 127. Namely, to avoid an electrical interference between the active pattern 122a and the pixel electrode 150, the pixel electrode 150 has a third distance d3, which is equal to the first distance d1 (of FIG. 2), from the active pattern 122a. Since the pixel electrode 150 should have a greater distance from the data line 127, a black matrix, which is disposed on a counter substrate, for preventing light leakage through a space between the pixel electrode 150 and the data line 127, should have a larger width. As a result, an aperture ratio is reduced.